In general, a plasma display panel (to be also abbreviated to PDP hereinafter) has many advantages, e.g., having a low profile, allowing large-screen display with relative ease, providing a wide viewing angle, and having a high response speed. Owing to these advantages, plasma display panels have recently been used as flat displays, wall-mounted TV sets, and public display boards. PDPs are classified into direct current discharge type (DC) PDPs and alternating current discharge type (AC) PDPs according to their operation schemes. A DC PDP is designed to operate in a direct current discharge state in which electrodes are exposed to a discharge space (discharge gas). An AC PDP is designed to operate in an alternating current discharge state in which electrodes are covered with dielectric layers and are not directly exposed to a discharge gas. In a DC PDP, discharge is caused during a period in which a voltage is applied. In an AC PDP, discharge is sustained by reversing the polarity of a voltage. In addition, AC PDPs include a PDP having two electrodes in one cell and a PDP having three electrodes in one cell.
The structure of a conventional three-electrode AC plasma display panel and a method of driving the panel will be described below. FIGS. 1 and 2 are plan and sectional views each showing an example of a conventional three-electrode AC plasma display panel. This three-electrode AC plasma display panel includes a front substrate 20 and rear substrate 21 which face each other, X electrodes 22, Y electrodes 23, and data (address) electrodes 29 which serve as display electrodes for surface discharge and are arranged between the two substrates 20 and 21, and display cells 31 (see FIG. 1) arranged at the intersections of the X electrodes 22, Y electrodes 23, and data electrodes 29 in the form of a matrix.
A glass substrate or the like is used as the front substrate 20. The X and Y electrodes 22 and 23 are arranged at predetermined intervals. Metal electrodes 32 are stacked on the X and Y electrodes 22 and 23 to decrease the wiring resistance. A transparent dielectric layer 24 and a protective layer 25 which is made of MgO or the like and protects the transparent dielectric layer 24 against discharge are formed on these electrodes. A glass substrate or the like is used as the rear substrate 21, on which the data electrodes 29 are arranged to cross the X and Y electrodes 22 and 23 at right angles. A white dielectric layer 28 and phosphor layer 27 are formed on the data electrodes 29. A plurality of partition walls 35 are formed parallel to each other at predetermined intervals between the two glass substrates. The partition walls 35 serve to ensure a discharge space 26 and separate pixels from each other. A gas mixture of He, Ne, Xe, and the like is sealed in the discharge space 26. Such a structure is disclosed in SID 98 DIGEST, pp. 279–281, May, 1998.
Referring to FIG. 1, reference numeral 30 denotes a display screen. Display cells 31 are arranged at the intersections of electrodes Xi (i=1 to m) as the X electrodes 22, Yi electrodes as the Y electrodes 23, and electrodes Dj (j=1 to n) as the data electrodes 29 in the form of a matrix.
A method of driving this three-electrode AC plasma display panel will be described next. Today, the dominating driving method is the ADS (Address/Display Separation) scheme of separating an address period from a sustain period (display period). A driving method based on this address/display separation scheme will be described below. FIG. 3 is a timing chart showing one sub-field 1 (to be abbreviated to SF hereinafter) in a three-electrode AC plasma display panel. One sub-field 1 is constituted by three periods, namely a priming (rest) period 2, address period 3, and sustain period 4.
The priming period 2 will be described first. Positive and negative priming pulses 5 and 6 are respectively applied to the X and Y electrodes 22 and 23. This produces a priming effect. That is, the difference between the formation state of wall charge at the end of the preceding SF and that of the current SF due to the emission state of the preceding SF is reset to achieve initialization, and all pixels are forced to discharge, thereby preparing for writing discharge at a low voltage afterward. Referring to FIG. 3, the positive and negative priming pulses 5 and 6 are applied once. In some cases, however, a sustain eliminating pulse for resetting the state of the preceding SF is applied first, and then a priming pulse for producing a priming effect by making all pixels discharge is applied. In this manner, pulses with two different roles may be separately applied. In this case, the number of times a sustain eliminating pulse is applied is not limited to one, and different pulses may be applied a plurality of number of times.
A priming effect is not always required for each SF. In some driving methods, therefore, a priming pulse is applied only once for every several SFs. Since a priming pulse causes all pixels to emit light regardless of display, the luminance in a black display period can be suppressed low by decreasing the number of times of application of a priming pulse. As in the prior art shown in FIG. 3, when the priming pulse 5 or 6 is to be used, in order to produce the priming effect of forcing all pixel to discharge once for every several SFs, the priming pulse 5 or 6 may be reduced in level to have only a resetting function in SFs other than the one shown in FIG. 3. In this case, different pulses may be applied a plurality of number of times instead of a priming pulse to reliably reset.
The address period 3 follows the priming period 2. In the address period 3, an address pulse 8 is sequentially applied to the electrodes X1 to Xm as the X electrodes 22. In synchronism with this address pulse 8, a data pulse 9 is applied to the electrodes D1 to Dn as the data electrodes 29 in accordance with a display pattern. In a pixel to which the data pulse 9 is applied, since a high voltage is applied between the X electrode 22 and the data electrode 29, writing discharge occurs to form a large amount of positive wall charge on the X electrode 22 side and negative wall charge on the data electrode 29 side. In a pixel to which no data pulse 9 is applied, since the applied voltage decreases, no discharge occurs, resulting in no change in wall charge state. As described above, two types of wall charge states can be produced depending on the presence/absence of the data pulse 9. The hatch lines corresponding to the data pulse 9 in FIG. 3 indicate that the data pulse 9 is present or absent depending on display data.
When application of the address pulse 8 to all electrode lines is complete, the address period 3 shifts to the sustain period 4. A sustain pulse 10 is alternately applied to all the X electrodes 22 and all the Y electrodes 23. The voltage of the sustain pulse 10 is set to a voltage at which no discharge is caused by the voltage itself. For this reason, in a pixel in which no writing discharge is caused, since wall discharge is small in amount, even if a sustain pulse is applied, no discharge occurs. In contrast to this, in a pixel in which writing discharge is caused, since a large amount of positive wall charge exists on the X electrode 22 side, this positive wall charge is superimposed on the first positive sustain pulse (to be referred to as the first sustain pulse) applied to the X electrode 22, thereby applying a voltage higher than the discharge start voltage in a discharge space. As a consequence, sustain discharge occurs. With this discharge, negative wall charge is stored on the X electrode 22 side, and positive wall charge is stored on the Y electrode 23 side.
The next sustain pulse (to be referred to as the second sustain pulse) is applied to the Y electrode 23 side. In this case as well, since the above wall charge is superimposed on this pulse, sustain discharge occurs, and wall charge having the opposite polarity to the first sustain pulse is stored on the X electrode 22 side and Y electrode 23 side. Subsequently, discharge continuously occurs on the same principle as described above. That is, the potential difference due to the wall charge produced by the xth sustain discharge is superimposed on the (x+1)th sustain pulse to maintain sustain discharge. The light emission amount is determined by the number of times this sustain discharge is maintained.
The above reset period 2, address period 3, and sustain period 4, which constitute a sustain eliminating period, will be referred to as a sub-field 1 as a whole. When gray-scale display is to be performed, one field which is a period in which one-frame image information is displayed is constituted by a plurality of sub-fields 1. The number of sustain pulses in each sub-field 1 is changed to turn on or off each sub-field 1, thereby performing gray-scale display.
In the above structure and driving method, however, a non-discharge gap 37, which is the distance between the X electrode of a given cell and the Y electrode of an adjacent cell as in FIG. 1, must be set to be larger than a discharge gap 36. Therefore, the above structure and method are not suited to a high-resolution panel. In contrast to this, as a known panel structure and driving method which are suited to high resolution, for example, the plasma display panel driving method and plasma display panel apparatus disclosed in Japanese Unexamined Patent Publication No. 9-160525 are available. FIG. 4 is a plan view of the panel. This panel differs from the conventional panel in FIG. 1 in that one Y electrode is additionally formed on the upper portion, and all X and Y electrodes are arranged at equal intervals. In the prior art shown in FIG. 4, pixels are formed in the electrode gaps between all the X and Y electrodes, thus making this structure suitable for a high-resolution screen.
FIGS. 5 and 6 show a driving method for another prior art shown in FIG. 4. FIG. 5 shows driving waveforms in an odd-numbered field in the prior art shown in FIG. 4. FIG. 6 shows driving waveforms in an even-numbered field in the prior art shown in FIG. 4. The operation in a priming period 2 is the same as that in the prior art shown in FIG. 3. An address period 3 follows the priming period 2. In the address period 3, an address pulse 8 is sequentially applied to electrodes X1 to Xm as X electrodes 22. In synchronism with this address pulse 8, a data pulse 9 is applied to electrodes D1 to Dn as data electrodes 29 in accordance with a display pattern. FIG. 7 shows how the data pulse 9 is applied in this case. Referring to FIG. 7, electrodes Y1 to X3 are placed in a line on a given data electrode in FIG. 4. In the case shown in FIG. 7, ON/OFF display like that indicated at the upper portion in the drawing is performed. This driving method is interlaced driving. Therefore, in an odd-numbered field, the first, third, and fifth pixels, viewed from the left, are displayed. In an even-numbered field, the second and fourth pixels are displayed.
An odd-numbered field will be described first. Since only the first pixel of the first, third, and fifth pixels is an ON pixel, the data pulse 9 is applied only when the address pulse 8 is applied to the electrode X1 as the X electrode 22 corresponding to the first pixel. When application of the address pulse 8 to all the lines is complete, the sustain period 4 starts. In an odd-numbered field, the odd-numbered X electrodes and even-numbered Y electrodes are in phase, and so are the even-numbered X electrodes and odd-numbered Y electrodes. For this reason, in a pixel in which wall charge is formed in an address period, sustain discharge occurs between the odd-numbered X electrode and the odd-numbered Y electrode and between the even-numbered X electrode and the even-numbered Y electrode. In the prior art shown in FIG. 7, although no sustain discharge occurs at the first sustain timing, sustain discharge starts from the second sustain timing and is maintained thereafter. When no wall charge is formed in odd- and even-numbered fields during an address period, no sustain discharge occurs.
An even-numbered field will be described next. Since both the second and fourth pixels are ON pixels, the data pulse 9 is applied at both timings at which the address pulse 8 is applied to the electrode X1 as the X electrode 22 corresponding to the second pixel and the electrode X2 as the X electrode 22 corresponding to the fourth pixel. When application of the address pulse 8 to all the lines is complete, the sustain period 4 starts. In an even-numbered field, the odd-numbered X electrode and odd-numbered Y electrode are in phase, and the even-numbered X electrode and even-numbered Y electrode are in phase. For this reason, in a pixel in which wall charge is formed during an address period, sustain discharge occurs between the odd-numbered X electrode and the odd-numbered Y electrode and between the even-numbered X electrode and the even-numbered Y electrode. In this case as well, although no sustain discharge occurs in the second pixel at the first sustain timing, sustain discharge starts from the second sustain timing as in an odd-numbered field and is maintained thereafter.
As described above, according to this driving method, by adding two fields, i.e., odd- and even-numbered fields, display can be performed between all the X and Y electrodes. This makes it possible to realize a high-resolution display.
As described above with reference to the first prior art, when progressive (non-interlaced) driving is to be used, only the discharge gaps between respective X and Y electrode pairs can be used for display. In contrast to this, when display is to be performed between all the X and Y electrodes, interlaced driving must be used.